Professor, Dean EAS

Office:  Engineering 201
Phone:  (719) 262-3551
Email: 
Home Page: http://eceweb.uccs.edu/rdan

Biographical Sketch

Professor Dandapani received his Bachelors degree from Indian Institute of Science in Bangalore, India and the M.S. and Ph.D. degrees from the University of Iowa, Iowa City. He joined the faculty at UCCS in 1986. Dr. Dandapani has been visiting academic at Stanford (California), Illinois (Champaign-Urbana), Iowa (Iowa City), Newcastle (Australia), and RMIT (Australia). Dr. Dandapani has been a consultant to a number of companies including Symbios Logic, Ford Motor Company, Sun Microsystems Inc, Ford Microelectronics Inc, United Technologies Microelectronics Center, and Digital Equipment Corporation. Dr. Dandapani has presented a number of short courses in his research area under the auspices of Institute of Electrical and Electronic Engineers,  American Society of Test Engineers, and Australian Electronics Development Centre. Dr. Dandapani was a member of the IEEE Working group that developed the IEEE 1149.4 Standard for mixed-signal testability bus.

Research

Dr. Dandapani’s research area is in testing and testable design of digital and analog circuits, boards, and systems.

Honors and Awards

1. Special Chancellor's Award
   For directing National Science Olympiad 2001
2. Patent Incentive Award from Ford Motor Company, 1997
   For the work "Optimum Test Set Generation for Mixed-Signal Boards"
3. Outstanding Teacher Award, 1996
   College of Engineering and Applied Science, Electrical and Computer Engineering Department
4. Motorola Silverkey Award, with Amit Majumder, 1993
   Awarded for Paper "Neural Networks as Massively Parallel Automatic Test Pattern Generators"
5. IEEE Region 5 Award, 1992
   Awarded for valued services as the IEEE Student Branch Counselor
6. Department of Electrical and Computer Engineering, 1990
   "Outstanding Among Faculty for Dedication and Teaching"

Selected Publications

1. Dave Stang and R. Dandapani, ?An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements,? Proceedings, IEEE International Test Conference, 2002
2. R. Dandapani, ?Testing and Testable Design of Circuits and Boards,? seminar presented at the School of Computer Science, University of Oklahoma, Oklahoma City, Oklahoma, March 2002
3. R. Dandapani, ? Test and Design for Testability, sponsored by Australian Electronics Development Centre, Melbourne, Australia, May 27-28 and Sydney, Australia, June 2-3, 1997
4. David Cheek and R. Dandapani, ?Integration of IEEE Std. 1149.1 and Mixed-Signal Test Architectures,? Proceedings, IEEE International Test Conference, 1995
5. W. Mao, Y. Lu, R. Gulati, R. Dandapani, and D. Goel, ?Test Generation for Linear Analog Circuits,? Proceedings, IEEE Custom Integrated Circuits Conference, 1995
6. J. Wallack and R. Dandapani, ?Coverage Metrics for Functional Tests,? Digest of Papers, 12th IEEE VLSI Test Symposium, 1994
7. Y. Lu and R. Dandapani, ?Hard Fault Diagnosis in Analog Circuits using Sensitivity Analysis,? Digest of Papers, 11th IEEE VLSI Test Symposium, 1993
8. A. Majumder and R. Dandapani, ?Neural Networks as Massively Parallel Automatic Test Pattern Generators,? Proceedings IEEE International Conference on Neural Networks, 1993
9. V. Chandramouli, R. Gulati, and R. Dandapani, ?A New BIST Scheme for CMOS PLAs,? Proceedings IEEE Custom Integrated Circuits Conference, 1993

Service

Panelist, DAC proposal reviews, NSF, Washington, D.C., February 5, 1999

Panelist, SBIR proposal reviews, NSF, Washington, D.C., September 10, 1997

IEEE 1149.4 Std. Mixed Signal Testability Bus Working Group, Member, January 1991-2000

Colorado Science Olympiad, Board of Directors, 1993-2008

National Science Olympiad 2001, Director

Colorado Science Olympiad, Southern Regional Director, 1992-2001, 2003-2008

Technical Program Committee Member, 1991 IEEE VLSI Test Symposium

For further details, go to Dr. Dandapani's Home Page